Airborne FPGA Certification
New advisory circular clarifies tool qualification requirements for synthesis and place-and-route tools used in DAL A and B FPGA designs. Addresses the growing gap between tool complexity and existing TQL definitions.
Updated tool qualification data for Vivado synthesis and implementation. Includes new coverage for UltraScale+ and Versal device families. Previous packages did not cover Versal NoC configuration flows.
CAST paper originally addressing multi-core processor interference is being applied by some DERs to FPGA designs with multiple independent clock domains. Implications for partitioning and independence arguments in complex SoC-class FPGAs.
Independent evaluation of the Xilinx Memory Interface Generator for use in certified designs. Vendor documentation covers functional behavior but leaves significant gaps in failure mode analysis and error injection coverage.
SC-180 committee is reviewing proposed supplements to DO-254 addressing modern FPGA architectures including adaptive SoCs and chiplet-based devices. Comment period open through May 15.
First compliance package for the Agilex 5 family. Covers synthesis, fitter, and timing analyzer. Does not yet include coverage for HPS subsystem integration paths.
EASA position on whether bitstream readback constitutes sufficient verification evidence for configuration integrity. Short answer: it depends on your DAL and your independence argument.