IP Corner
Independent evaluation of FPGA IP cores for DO-254 certification readiness. What vendors provide, what's missing, and what you'll need to build yourself.
Vendor IP cores are treated as COTS components under DO-254. Each requires a usage domain analysis, configuration documentation, and verification coverage independent of the vendor's claims. These evaluations assess what the vendor actually provides versus what your certification program will require.
MIG generates DDR3/DDR4 memory controllers with calibration logic. Functional documentation is adequate for design integration. However, failure mode documentation is sparse — error injection paths, calibration timeout behavior, and multi-bit ECC failure responses are not characterized in vendor documentation. Verification burden falls entirely on the integrator at DAL B and above.
Vendor Documentation
Functional behavior covered. Timing constraints provided. Error handling behavior undocumented.
Certification Gap
No failure mode analysis. No fault injection guidance. Calibration sequence not traceable to requirements.
Effort Estimate
4–8 weeks additional verification at DAL C. 8–16 weeks at DAL B/A including independent fault analysis.
Recommendation
Usable at DAL C with supplemental verification. At DAL A/B, consider whether a custom controller with full traceability is more cost-effective.
Evaluated: Apr 2026
MMCM/PLL clock generation and management. Well-documented functional behavior. Lock detection timing is specified but lock-loss behavior under transient conditions is not fully characterized. Configuration via DRP adds complexity to the verification argument — dynamic reconfiguration paths must be treated as separate operating modes.
Vendor Documentation
Good functional coverage. Lock timing specified. DRP interface documented but usage domain implications not addressed.
Certification Gap
Lock-loss transient behavior. DRP reconfiguration safety. No vendor-provided FMEA for clock failure modes.
Effort Estimate
2–4 weeks at DAL C. Primarily clock domain analysis and lock-loss response verification.
Recommendation
Widely used in certified designs. Manageable at all DAL levels with proper usage domain analysis. Avoid DRP reconfiguration in safety-critical paths.
Evaluated: Apr 2026
High-speed serial transceivers are among the most complex IP blocks in any FPGA. The number of configuration parameters, the interaction between analog and digital subsystems, and the protocol-dependent behavior make transceiver IP one of the highest-effort items for DO-254 qualification. Vendor documentation covers functional configuration but does not address failure modes at the level required for DAL A/B programs.
Vendor Documentation
Configuration guides extensive. Protocol compliance data available. Analog behavior (eye margin, jitter) characterized but not in certification-ready format.
Certification Gap
No FMEA for link failure modes. CDR lock acquisition/loss not characterized for safety analysis. Hundreds of configuration attributes require usage domain justification.
Effort Estimate
8–20 weeks depending on protocol and DAL. Per-protocol effort — JESD204C, Aurora, and custom protocols each require independent verification campaigns.
Recommendation
Budget significant effort. Engage someone with transceiver architecture experience. Do not attempt usage domain analysis from documentation alone — hands-on characterization is required.
Evaluated: Apr 2026
Additional IP evaluations in progress. Upcoming: Altera IOPLL, Microchip Math Block, Xilinx AXI Interconnect.
Airborne FPGA Certification